1. Field of the Invention
The present invention relates to a semiconductor chip package structure in which a semiconductor chip is mounted on a wiring substrate by flip chip bonding to a wiring pattern on the wiring substrate.
2. Description of the Related Art
Recent progress of miniaturization and density of semiconductor devices is leading to dense packages by using a semiconductor chip package structure in which a semiconductor chip is mounted on a wiring substrate by flip chip bonding to a wiring pattern on the wiring substrate, such as that presented by a BGA (ball grid array) type semiconductor device. Generally, a wiring substrate has one surface with a semiconductor chip mounted thereon by flip chip bonding to a wiring pattern formed on that surface, and has the other surface with external connector terminals formed thereon and electrically connected to the wiring pattern.
FIG. 1 shows a conventional BGA type semiconductor device.
A semiconductor device 11 is basically composed of a semiconductor chip 12, solder bumps 13 as a electrode terminal of the semiconductor chip, a wiring substrate 14, an underfiller 19, and solder balls 17 as an external connector terminal of the wiring substrate 14. The semiconductor device 11 is mounted on a motherboard 18 by bonding the solder balls 17 to the motherboard 18 to complete a package structure.
The semiconductor chip 12 is mounted on one surface 14a of the wiring substrate 14. The solder bumps 13 are formed as an electrode terminal on a surface 12a of the semiconductor chip 12 and are electrically connected to wiring patterns 14c on the surface 14a of the wiring substrate 14. The solder bumps 13 are formed, for example, by forming a mask on the surface 12a of the semiconductor chip 12, followed by solder plating. This provides a large number of electrode terminals 13 in the form of solder bumps on the surface 12a.
The semiconductor chip 12 is placed on the surface 14a of the wiring substrate 14 and the solder bumps 13 are bonded to the wiring patterns 14c to leave a space between the surface 12a of the semiconductor chip 12 and the surface 14a of the wiring substrate 14 in the regions other than the bonded regions. The underfiller 19 is formed by filling the space with an insulating epoxy resin, for example.
Pads (not shown) are formed on the other surface 14b of the wiring substrate 14 and are electrically connected to the wiring patterns 14c on the opposite surface 14a through a plated portion of throughholes (not shown) extending through the wiring substrate. The pads have the solder balls 17 formed thereon as an external connector terminal.
The semiconductor device 11 is placed on the motherboard 18 with the solder balls 17 of the semiconductor device 11 being in contact with the lands 18a of the motherboard 18 to mount the semiconductor device 11 on the motherboard 18, thereby completing the package structure shown in FIG. 1.
Generally, the wiring substrate 14 and the motherboard 18 are made of an organic material (resin) of the same or a similar kind and have the same or a similar heat expansion coefficient. The wiring substrate 14, on which the semiconductor chip 12 is directly mounted, is suitably and frequently an organic material substrate such as a flexible substrate of a double sided copper clad laminate substrate. These organic materials generally have a relatively low stiffness.
In comparison with these organic materials, the semiconductor chip 12 mounted on the wiring substrate by being fixed with an underfiller has a very high stiffness and, on the other hand, a low thermal expansion coefficient.
Therefore, when the heating is effected for mounting the semiconductor device 11 on the motherboard 18, the wiring substrate 14 is prevented from free displacement by the semiconductor chip 12 having a far greater stiffness and exhibits a thermal expansion as small as that of the semiconductor chip 12 to cause an apparent difference in thermal expansion with respect to the motherboard 18 exhibiting a relatively great thermal expansion which is a characteristic of an organic material. This generates a stress concentrated at the bonds of the solder balls 17 to lower the reliability of the bond between the solder balls 17 of the wiring substrate 14 and the pads 18a of the motherboard 18. The thus-generated thermal stress cannot be mitigated by the underfiller 19 formed of an insulating resin filled and cured in between the wiring substrate 14 and the semiconductor chip 12.
Moreover, a thermal expansion difference between the semiconductor chip 12 and the wiring substrate 14 lowers the reliability of the bond between the solder bumps 13 as an external terminal of the semiconductor chip 12 and the wiring patterns 14c on the wiring substrate 14.
These phenomena become more significance as the semiconductor chip 12 becomes denser and the wiring substrate 14 is enlarged.
Forming of the solder bumps 14 on the electrode terminal arrangement surface 12a of the semiconductor chip 12 requires complicated process steps including forming an UBM (under bump metal) on the surface 12a and plating of the surface 12a, which unavoidably raises the production cost.